參數(shù)資料
型號(hào): X4C105
廠商: Intersil Corporation
元件分類: CPU監(jiān)測(cè)
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁(yè)數(shù): 9/19頁(yè)
文件大?。?/td> 296K
代理商: X4C105
9
FN8124.0
March 18, 2005
Figure 11. Sequential Read Sequence
After loading the entire slave address byte from the
SDA bus, the device compares the device select bits
with the status of the device select pins. Upon a cor-
rect compare, the device outputs an acknowledge on
the SDA line.
Slave Byte
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Write Protect Operations
The WP pin provides write protection. The WP pin pro-
tects the upper half of the array.
Table 1. Write Protected Areas
S
t
o
p
A
C
K
A
C
K
A
C
K
Data
(2)
Slave
Address
Data
(n)
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
(n is any integer greater than 1)
Data
(1)
1
0
1
0
S2
S1
A8
R/W
WP Pin
LOW
HIGH
Serial Memory Write Protection
Writes possible to all locations
No writes to 100H-1FFH, writes possible
to 000H to 0FFH
X4C105
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