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參數(shù)資料
| 型號： | X4283S8-2.7 |
| 元件分類： | EEPROM |
| 英文描述： | CPU Supervisor with 128K EEPROM |
| 中文描述： | CPU監(jiān)控與128K的EEPROM的 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 412K |
| 代理商： | X4283S8-2.7 |
X4283/85 – Preliminary Information
Characteristics subject to change without notice.
7 of 22
REV 1.17 11/27/00
www.xicor.com
Table 1. Write Protect Enable Bit and WP Pin Function
WP
LOW
HIGH
HIGH
WPEN
X
0
1
Memory Array not
Block Protected
Writes OK
Writes OK
Writes OK
Memory Array
Block Protected
Writes Blocked
Writes Blocked
Writes Blocked
Block Protect
Bits
Writes OK
Writes OK
Writes Blocked
WPEN Bit
Writes OK
Writes OK
Writes Blocked
Protection
Software
Software
Hardware
Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be repre-
sented as
0xys t
01
r
in binary, where
xy
are the WD
bits, and
rst
are the BP bits. (Operation preceded by a
start and ended with a stop). Since this is a nonvola-
tile write cycle it will take up to 10ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (
0xys t
11
r
) then the
RWEL bit is set, but the WD1, WD0, BP2, BP1 and
BP0 bits remain unchanged. Writing a second byte to
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
– A read operation occurring between any of the previous
operations will not interrupt the register write operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto
the bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the
slave. The master always initiates data transfers, and
provides the clock for both transmit and receive opera-
tions. Therefore, the devices in this family operate as
slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
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