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參數(shù)資料
| 型號： | X4283S8-2.7 |
| 元件分類： | EEPROM |
| 英文描述： | CPU Supervisor with 128K EEPROM |
| 中文描述： | CPU監(jiān)控與128K的EEPROM的 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 412K |
| 代理商： | X4283S8-2.7 |
X4283/85 – Preliminary Information
Characteristics subject to change without notice.
3 of 22
REV 1.17 11/27/00
www.xicor.com
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4283/85 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
TRIP
threshold value
LOW VOLTAGE MONITORING
During operation, the X4283/85 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
TRIP
for 200ms.
CC
level
TRIP
. The RESET/RESET
CC
returns and exceeds
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL is HIGH (this is a start bit) prior
to the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvola-
tile control bits in the Status Register determine the
watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “l(fā)ocked” by tying
the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
THRESHOLD RESET PROCEDURE
The X4283/85 is shipped with a standard V
old (V
TRIP
) voltage. This value will not change over nor-
mal operating and storage conditions. However, in
applications where the standard V
right, or if higher precision is needed in the V
value, the X4283/85 threshold may be adjusted. The
procedure is described below, and uses the application
of a nonvolatile control signal.
CC
thresh-
TRIP
is not exactly
TRIP
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
0 1 2 3 4 5 6 7
SCL
SDA
A0h
0 1 2 3 4 5 6 7
00h
WP
V
P
= 12-15V
0 1 2 3 4 5 6 7
01h
0 1 2 3 4 5 6 7
00h
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