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參數(shù)資料
| 型號： | X4165V8-2.7 |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 496K |
| 代理商： | X4165V8-2.7 |
X4163/5
Characteristics subject to change without notice.
3 of 22
REV 1.32 5/27/04
www.xicor.com
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4163/5 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benets.
– It prevents the system microprocessor from starting
to operate with insufcient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its congura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP threshold value
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4163/5 monitors the VCC level
and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL is HIGH (this is a start bit) prior
to the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvola-
tile control bits in the Status Register determine the
watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “l(fā)ocked” by tying
the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress
communications
are
terminated.
While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to nish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC THRESHOLD RESET PROCEDURE
The X4163/5 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X4163/5 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
012 345 67
SCL
SDA
A0h
012 345 67
00h
WP
VP = 12-15V
012 345 67
01h
012 345 6 7
00h
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| X4165V8I | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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