參數(shù)資料
型號: X4165V8-2.7
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: PLASTIC, TSSOP-8
文件頁數(shù): 12/22頁
文件大小: 496K
代理商: X4165V8-2.7
X4163/5
Characteristics subject to change without notice.
2 of 22
REV 1.32 5/27/04
www.xicor.com
PIN CONFIGURATION
S1
VSS
VCC
SDA
SCL
3
2
4
1
6
7
5
8
8-Pin JEDEC SOIC
S0
WP
RESET/RESET
VCC
S1
SCL
RESET/RESET
VSS
3
2
4
1
6
7
5
8
WP
SDA
S0
8 Pin TSSOP
PIN FUNCTION
Pin
(SOIC)
Pin
(TSSOP)
Name
Function
13
S0
Device Select Input
24
S1
Device Select Input
35
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 250ms. RESET/
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes ac-
tive on power up and remains active for 250ms after the power supply stabilizes.
46
VSS
Ground
57
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the de-
vice. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
68
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
71
WP
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
82
VCC
Supply Voltage
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