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參數(shù)資料
| 型號： | X4163S8Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 342K |
| 代理商： | X4163S8Z |
5
FN8120.2
November 26, 2007
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4163, X4165 activates a
Power On Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
It prevents the system microprocessor from starting to
operate with insufficient voltage.
It prevents the processor from operating prior to stabilization
of the oscillator.
It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
It prevents communication to the EEPROM, greatly reducing
the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP threshold value for
200ms (nominal) the circuit releases RESET/RESET allowing
the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4163, X4165 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
microprocessor must periodically send a start bit followed by
a stop bit prior to the expiration of the watchdog time out
period to prevent a RESET/RESET signal. The start and
stop bits need to be separated by SCL toggling low then high
at least one time.
The state of two nonvolatile control bits in the Status
Register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be “l(fā)ocked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC THRESHOLD RESET PROCEDURE
The X4163, X4165 is shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard VTRIP is not
exactly right, or if higher precision is needed in the
VTRIP value, the X4163, X4165 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
01 2 3 45 67
SCL
SDA
A0h
01 2 3 45 67
00h
WP
VP = 12-15V
01 2 3 45 67
01h
01 2 3 4 5 6 7
00h
X4163, X4165
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X4163S8Z-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 16K EEPROM |
| X4163S8Z-2.7A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 16K EEPROM |
| X4163S8Z-4.5A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 16K EEPROM |
| X4163V8 | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X4163V8-2.7 | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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