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| 型號(hào)： | X4043S8IZ-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | GREEN, PLASTIC, SOIC-8 |
| 文件頁(yè)數(shù)： | 3/25頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | X4043S8IZ-2.7 |
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X4043/45
Characteristics subject to change without notice.
3 of 25
REV 1.1.17 9/14/01
www.xicor.com
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4043/45 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V
CC
exceeds the device V
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
TRIP
threshold value
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
TRIP
for 200ms.
CC
level
TRIP
. The RESET/RESET
CC
returns and exceeds
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “l(fā)ocked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V
CC
< V
TRIP
munications are terminated. While V
new communications are allowed and no nonvolatile
write operation can start. Nonvolatile writes in-progress
when RESET/RESET goes active are allowed to finish.
), any in-progress com-
< V
CC
TRIP
, no
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X4043/45 is shipped with a standard V
old (V
TRIP
) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V
right, or if higher precision is needed in the V
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the application
of a high voltage control signal.
TRIP
Programming
CC
thresh-
TRIP
is not exactly
TRIP
SCL
SDA
.6μs
1.3μs
Start
Stop
Reset
WDT
Figure 2. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
0
1
2 3
4
5 6
7
SCL
SDA
A0h
0
1
2 3
4
5 6
7
01h
WP
V
P
= 15-18V
0
1
2 3
4
5 6
7
00h
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