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參數(shù)資料
| 型號： | X4043S8IZ-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 144K |
| 代理商： | X4043S8IZ-2.7 |
X4043/45
Characteristics subject to change without notice.
11 of 25
REV 1.1.17 9/14/01
www.xicor.com
Figure 14. Current Address Read Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5kHz write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal nonvolatile cycle. Acknowledge
polling can be initiated immediately. To do this, the mas-
ter issues a start condition followed by the slave
address byte for a write or read operation. If the device
is still busy with the nonvolatile cycle then no ACK will
be returned. If the device has completed the write oper-
ation, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to the
flow chart in Figure 13.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the slave address byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the data byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.
Figure 13. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition dur-
ing the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
ACK
Returned
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Nonvolatile Cycle
Complete. Continue
Command
Issue STOP
NO
Continue Normal
Read or Write
Command Sequence
PROCEED
YES
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