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參數(shù)資料
| 型號(hào)： | X40030 |
| 廠商： | Intersil Corporation |
| 英文描述： | Thyristor Diode Module; Repetitive Reverse Voltage Max, Vrrm:100V; Current Rating:325A |
| 中文描述： | 三電壓監(jiān)視器集成CPU監(jiān)控 |
| 文件頁(yè)數(shù)： | 18/21頁(yè) |
| 文件大?。?/td> | 322K |
| 代理商： | X40030 |
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18
FN8114.0
April 28, 2005
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V
CC
= 5V)
Notes: (1) V
CC
= 5V at 25°C.
(2) Values based on characterization data only.
Watchdog Time Out For 2-Wire Interface
Symbol
t
RPD1(2)
t
RPDL
t
LR
t
RPDX(2)
t
PURST
Parameters
Min.
Typ.
(1)
Max.
5
Unit
μs
V
TRIP1
to RESET/RESET (Power down only)
V
TRIP1
to LOWLINE
LOWLINE to RESET/RESET delay (Power down only) [= t
RPD1
-t
RPDL
]
V
TRIP2
to V2FAIL, or V
TRIP3
to V3FAIL (x = 2, 3)
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
500
ns
μs
5
50
(2)
200
400
(2)
800
(2)
ms
ms
ms
ms
t
F
t
R
V
CC,
V2MON
,
V3MON
,
Fall Time
V
CC,
V2MON
,
V3MON
,
Rise Time
Reset Valid V
CC
MR to RESET/ RESET delay (activation only)
Pulse width for MR
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1 = 1, WD0 = 1 (factory setting)
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
20
20
1
500
5
mV
/
μs
mV
/
μs
V
ns
μs
V
RVALID
t
MD
t
in1
t
WDO
1.4
(2)
200
(2)
25
OFF
200
s
ms
ms
t
RST1
100
300
ms
t
RST2
t
RSP
12.5
1
25
37.5
ms
μs
< t
WDO
t
RST
WDO
SDA
Start
t
WDO
t
RST
SCL
Start
t
RSP
WDT
Restart
Start
SDA
SCL
Minimum Sequence to Reset WDT
Clockin (0 or 1)
X40030, X40031, X40034, X40035
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| X40030B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40030C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
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