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參數(shù)資料
| 型號(hào)： | X28HT512 |
| 英文描述： | High Temperature, 5 Volt, Byte Alterable EEPROM(工作溫度可達(dá)170℃，5V，字節(jié)可改變的EEPROM) |
| 中文描述： | 高溫，5伏，可變字節(jié)的EEPROM（工作溫度可達(dá)170℃，5V的，字節(jié)可改變的EEPROM中） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 135K |
| 代理商： | X28HT512 |
X28HT512
3
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X28HT512 supports both a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE
,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either
CE
or
WE
, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28HT512 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28HT512 prior to the
commencement of the internal programming cycle. The
host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A
7
through A
15
) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE
HIGH to LOW transition, must begin within 100
μ
s of
the falling edge of the preceding
WE
. If a subsequent
WE
HIGH to LOW transition is not detected within
100
μ
s, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100
μ
s.
HARDWARE DATA PROTECTION
The X28HT512 provides three hardware features that
protect nonvolatile data from inadvertent writes.
Noise Protection—A
WE
pulse typically less than
10ns will not initiate a write cycle.
Default V
CC
Sense—All write functions are inhibited
when V
CC
is
≤
3.4V.
Write Inhibit—Holding either
OE
LOW,
WE
HIGH,
or
CE
HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SYSTEM CONSIDERATIONS
Because the X28HT512 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.
It has been demonstrated that markedly higher tem-
perature performance can be obtained from this device
if
CE
is left enabled throughout the read and write
operation.
To gain the most benefit it is recommended that
CE
be
decoded from the address bus and be used as the
primary device selection input. Both
OE
and
WE
would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HT512 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling
CE
will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1
μ
F high fre-
quency ceramic capacitor be used between V
CC
and
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7
μ
F electrolytic
bulk capacitor be placed between V
CC
and V
SS
for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
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| X28HT512D-20 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:High Temperature, 5 Volt, Byte Alterable E2PROM |
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| X28HT512F-25 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:High Temperature, 5 Volt, Byte Alterable E2PROM |
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