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參數(shù)資料
| 型號： | X25383 |
| 英文描述： | Selectable Timeout Watchdog & VCC Supervisory Circuit & Serial EEPROM(具有串行EEPROM的可選超時周期看門狗監(jiān)控電路) |
| 中文描述： | 可選的超時看門狗 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 90K |
| 代理商： | X25383 |
X25383/85
3
PRINCIPLES OF OPERATION
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.
The device monitors the bus and asserts RESET/RESET
output if there is no bus activity within user selctable time-
out period or the supply voltage falls below a preset mini-
mum V
trip
. The device contains an 8-bit instruction regis-
ter. It is accessed via the SI input, with data being clocked
in on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
(
Table 1), addresses and data are trans-
Write Enable Latch
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
Status Register/IDLock/WDT Byte
IDLock Memory
Xicor’s IDLock Memory provides a flexible mechanism to
store and lock system ID and parametric information.
There are seven distinct IDLock Memory areas within the
array which vary in size from one page to as much as half
of the entire array. These areas and associated address
ranges are IDLocked by writing the appropriate two byte
IDLock instruction to the device as described in Table 1
and Figure 7. Once an IDLock instruction has been com-
pleted, that IDLock setup is held in the nonvolatile Status
Register until the next IDLock instruction is issued. The
sections of the memory array that are IDLocked can be
read but not written until IDLock Protection is removed or
changed.
Watchdog Timer
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Read Sequence
When reading from the E
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the 16-
bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest address
is reached, the address counter rolls over to address
$0000 allowing the read cycle to be continued indefinitely.
The read operation is terminated by taking CS high. Refer
to the Read E
PROM Array Sequence (Figure 1).
2
PROM memory array, CS is
2
To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
To write data to the E
issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused
address bits are specified to be “0’s”. The WRITE opera-
tion minimally takes 32 clocks. CS must go low and
remain low for the duration of the operation. If the address
counter reaches the end of a page and the clock contin-
2
PROM memory array, the user then
7
0
6
0
5
0
4
3
2
1
0
WD1
WD0
IDL2
IDL1
IDL0
Status Register Bits
WD1
0
0
1
1
Watchdog Time-out
(Typical)
1.4 Seconds
600 Milliseconds
200 Milliseconds
Disabled
WD0
0
1
0
1
相關PDF資料 |
PDF描述 |
|---|---|
| X25385 | Selectable Timeout Watchdog & V CC Supervisory Circuit w/Serial E 3 PROM(可選超時看門狗監(jiān)控電路) |
| X25640S | IC-SM-64K SERIAL EEPROM+SPI |
| X25330S8 | SPI Serial EEPROM |
| X25330S8I | SPI Serial EEPROM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X25383S8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25383S8-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25383S8-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25383S8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25383S8I-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
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