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參數(shù)資料
| 型號： | X24640S8I |
| 英文描述： | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| 中文描述： | 400kHz的2線串行E的2座鎖胎膜早破 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 85K |
| 代理商： | X24640S8I |
X24640
7
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the
internal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to figure 7.
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
ACK
RETURNED
HIGH
VOLTAGE
CYCLE COMPLETE.
CONTINUE
SEQUENCE
CONTINUE NORMAL
READ ORWRITE
COMMAND SEQUENCE
PROCEED
ISSUE STOP
NO
YES
YES
ISSUE STOP
NO
7038 FM 09
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 8 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
FROM THE
SLAVE
S
T
A
R
T
S
SLAVE
ADDRESS
S
T
O
P
P
A
C
K
DATA
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
1
0 1 0
1
7038 FM 10
Figure 7. Acknowledge Polling Sequence
Figure 8. Current Address Read Sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24640V20-2.5 | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640V20I-2.5 | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640S8I-2.5 | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640P-2.5 | 400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24641S8I-1.8 | 400 KHz 2-Wire Serial E 2 PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24640S8I-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640S8I-2.5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640V20 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640V20-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400KHz 2-Wire Serial E 2 PROM with Block Lock |
| X24640V20-2.5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400KHz 2-Wire Serial E 2 PROM with Block Lock |
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