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參數(shù)資料
| 型號： | X24012PIG-3 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | Serial E2PROM |
| 中文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 284K |
| 代理商： | X24012PIG-3 |
X24012
5
MASTER
SDA LINE
XX24012
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0
SDA LINE
X24012
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24012 this is fixed as
1010[B].
Following the start condition, the X24012 monitors the SDA
bus comparing the slave address being transmit-
ted with its slave address (device type and state of A
0
, A
1
and A
2
inputs). Upon a correct compare the X24012
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24012 will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24012 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
128 words of memory. Note: the most significant bit
is a don’t care. Upon receipt of the word address the
X24012 responds with an acknowledge, and awaits the
next eight bits of data, again responding with an ac-
knowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24012 begins
the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24012
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
Figure 4. Slave Address
The next three significant bits address a particular device.
A system could have up to eight X24012 devices
on the bus (see Figure 10). The eight addresses are defined
by the state of the A
0
, A
1
and A
2
inputs.
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
Figure 6. Page Write
1
0
1
0
A2
A1
A0
R/W
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
3847 FHD F08
3847 FHD F09
3847 FHD F10
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
BUS
BUS ACTIVITY:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24012PMG | Serial E2PROM |
| X24012PMG-2.7 | Serial E2PROM |
| X24012PMG-3 | Serial E2PROM |
| X24012SG | TRIAC,TG35E60,35A,600V FAST-ON PACKAGE |
| X24012SG-2.7 | Serial E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24012PM | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24012PM-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24012PM-3 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24012PMG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24012PMG-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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