參數(shù)資料
型號: X24012PIG-3
廠商: IC MICROSYSTEMS SDN BHD
元件分類: DRAM
英文描述: Serial E2PROM
中文描述: 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
封裝: ROHS COMPLIANT, PLASTIC, DIP-8
文件頁數(shù): 3/14頁
文件大?。?/td> 284K
代理商: X24012PIG-3
X24012
3
DEVICE OPERATION
The X24012 supports a bidirectional bus oriented proto- col.
The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore, the
X24012 will be considered a slave in all
applications
.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24012 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
SCL
SDA
DATA STABLE
DATA
CHANGE
SCL
SDA
START BIT
STOP BIT
3847 FHD F05
3847 FHD F06
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