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參數(shù)資料
| 型號(hào)： | X1288S16T1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/27頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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14
FN8102.3
April 14, 2006
Table 6. Digital Trimming Registers
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance
adjustment. Using a Citizen CFS-206 crystal with differ-
ent ATR bit combinations provides an estimated ppm
range from +116ppm to -37ppm to the nominal fre-
quency compensation. The combination of digital and
analog trimming can give up to +146ppm adjustment.
The on-chip capacitance can be calculated as follows:
CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF
Note that the ATR values are in two’s complement, with
ATR(000000) = 11.0pF, so the entire range runs from
3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application section and Intersil’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded
by a start and ended with a stop).
– Write a 06h to the Status Register to set both the Reg-
ister Write Enable Latch (RWEL) and the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceeded by a start and ended
with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is ter-
minated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is reset
by the completion of a nonvolatile write cycle, so the
sequence must be repeated to again initiate another
change to the CCR contents. If the sequence is not
completed for any reason (by sending an incorrect
number of bits or sending a start instead of a stop, for
example) the RWEL bit is not reset and the device
remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write oper-
ation.
POWER-ON RESET
Application of power to the X1288 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabili-
zation of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP threshold value for
typically, 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended VCC slew rate
is between 0.2V/ms and 50V/ms.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 differ-
ent time out periods or off. When the Watchdog timer is
set to off, the watchdog circuit is configured for low power
operation.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high and followed by a stop bit. The
start signal restarts the watchdog timer counter, resetting
the period of the counter back to the maximum. If another
start fails to be detected prior to the watchdog timer expi-
ration, then the RESET pin becomes active. In the event
that the start signal occurs during a reset time out period,
the start will have no effect. When using a single START
to refresh watchdog timer, a STOP bit should be followed
to reset the device back to stand-by mode.
DTR Register
Estimated frequency
PPM
DTR2
DTR1
DTR0
00
0
01
0
+10
00
1
+20
01
1
+30
10
0
11
0
-10
10
1
-20
11
1
-30
X1288
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