FN8101.1 April 14, 2006 Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is upda" />
參數(shù)資料
型號(hào)： X1286V14I
廠商： Intersil
文件頁(yè)數(shù)： 2/25頁(yè)
文件大?。?/td> 0K
描述： IC RTC/CAL/CPU SUP EE 14-TSSOP
標(biāo)準(zhǔn)包裝： 95
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS:hh（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
10
FN8101.1
April 14, 2006
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Range
Def
a
ult
7
6
54
321
0
(optional)
003F
Status
SR
BAT
AL1
AL0
0
RWEL
WEL
RTCF
01h
0037
RTC
(SRAM)
SSEC
SS23
SS22
SS21
SS20
SS13
SS12
SS11
SS10
0-99
xxh
0036
DW
0
DY2
DY1
DY0
0-6
xxh
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
xxh
0034
MO
0
G20
G13
G12
G11
G10
1-12
xxh
0033
DT
0
D21
D20
D13
D12
D11
D10
1-31
xxh
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
xxh
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
xxh
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
xxh
0013
Control
(EEPROM)
DTR
0
DTR2
DTR1
DTR0
00h
0012
ATR
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
Read Only Read Only Read Only
00h
0010
BL
BP2
BP1
BP0
WD1
WD0
Read Only Read Only Read Only
00h
000F
Alarm1
(EEPROM)
Y2K1
Read-only - Default = 20h
20
20h
000E
DWA1
EDW1
0
DY2
DY1
DY0
0-6
00h
000D
YRA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C
MOA1
EMO1
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
X1286
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