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參數資料
| 型號： | X1205V8IZT1 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2-Wire RTC Real Time Clock/Calendar |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8 |
| 文件頁數： | 10/22頁 |
| 文件大?。?/td> | 407K |
| 代理商： | X1205V8IZT1 |
PRELMNARY
Figure 8. Current Address Read Sequence
X1205 – Preliminary Information
REV 1.0.9 8/29/02
Characteristics subject to change without notice.
10 of 22
www.xicor.com
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1205 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1205 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1205 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1205 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 9.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1205 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1205 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 8 for the address,
acknowledge, and data transfer sequence.
Figure 9. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
ACK
returned
Issue Slave
Address Byte
(Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
Issue STOP
NO
Continue normal
Read or Write
sequence
PROCEED
YES
nonvolatile write
Cycle complete. Continue
command sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
1
1
1
1
1
0
1
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