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參數(shù)資料
| 型號： | WV3HG264M72EEU806D7SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, DMA244 |
| 封裝： | ROHS COMPLIANT, MINI, DIMM-244 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 221K |
| 代理商： | WV3HG264M72EEU806D7SG |
WV3HG264M72EEU-D7
May 2006
Rev. 0
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
VCC = +1.8V ± 0.1V
Parameter
Symbol
806
665
534
403
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Clock cycle time
CL=6
tCK(6)
TBD
CL=5
tCK(5)
TBD
3000
8000
----
ps
CL=4
tCK(4)
TBD
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK(3)
TBD
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
TBD
MIN(tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
ps
Clock jitter
tJIT
TBD
-125
125
-125
125
-125
125
ps
Data
DQ output access time from CK/CK#
tAC
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
TBD
tAC(MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
TBD
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
ps
DQ and DM input setup time relative to DQS
tDS
TBD
100
150
DQ and DM input hold time relative to DQS
tDH
TBD
175
225
275
DQ and DM input pulse width (for each input)
tDIPW
TBD
0.35
tCK
Data hold skew factor
tQHS
TBD
340
400
450
ps
DQ-DQS hold, DQS to rst DQ to go nonvalid, per
access
tQH
TBD
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
TBD
tQH
- tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
ns
Data
Strobe
DQS input high pulse width
tDQSH
TBD
0.35
tCK
DQS input low pulse width
tDQSL
TBD
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising - setup time
tDSS
TBD
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
TBD
0.2
tCK
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDQSQ
TBD
240
300
350
ps
DQS read preamble
tRPRE
TBD
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
TBD
000
ps
DQS write preamble
tWPRE
TBD
0.35
tCK
DQS write postamble
tWPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to rst DQS latching transition
tDQSS
TBD
WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25
tCK
AC specication is based on SAMSUNG components. Other DRAM manufacturers specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3HG264M72EEU806PD4IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL |
| WV3HG264M72EEU806PD4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL |
| WV3HG264M72EEU806PD4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL |
| WV3HG264M72EEU806PD4SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL |
| WV3HG264M72EEU-D6 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED |
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