參數(shù)資料
型號(hào): WV3HG264M72EEU534D4-SG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.5 ns, DMA200
封裝: ROHS COMPLIANT, SO-DIMM-200
文件頁數(shù): 8/10頁
文件大小: 160K
代理商: WV3HG264M72EEU534D4-SG
WV3HG264M72EEU-D4
August 2005
Rev. 0
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS (continued)
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
534
403
Units
min
max
min
max
Write recovery time
tWR
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
—tWR+tRP
—tCK
Internal write to read command delay
tWTR
7.5
10
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read command
tXP
2—2—
tCK
Exit active power down to read command
tXARD
2—2—
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
CKE minimum pulse width (high and low pulse width)
tCKE
33
tCK
ODT turn-on delay
tAOND
2222
tCK
ODT turn-on
tAON
tAC(min)
tAC(max) +1
tAC(min)
tAC(max) +1
ns
ODT turn-on (Power-Down mode)
tAONPD
tAC(min) +2
2tCK +tAC
(max) +1
tAC(min) +2
2tCK +tAC
(max) +1
ns
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)
+0.6
tAC(min)
tAC(max)
+0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min) +2
2.5tCK
+tAC(max)
+1
tAC(min) +2
2.5tCK
+tAC(max)
+1
ns
ODT to power down entry latency
tANPD
33
tCK
ODT power down exit latency
tAXPD
88
tCK
OCD drive mode output delay
tOIT
012012
ns
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK +tIH
ns
NOTE: AC timing parameters are based on Samsung components. Other DRAM manufacturers parameters may be different.
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