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參數(shù)資料
| 型號(hào)： | WV3HG264M72EEU534D4-SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.5 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 160K |
| 代理商： | WV3HG264M72EEU534D4-SG |
WV3HG264M72EEU-D4
August 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
534
403
Units
min
max
min
max
DQ output access time from CK/CK#
tAC
-500
+500
-600
+600
ps
DQS output access time from CK/CK#
tDQSCK
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min (tCL, tCH)
x
min (tCL, tCH)x
ps
Clock cycle time, CL=x
tCK
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH
225x275x
ps
DQ and DM input setup time
tDS
100x150x
ps
Control & Address input pulse width for each input
tIPW
0.6
—
0.6
—
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
—
0.35
—
tCK
Data-out high-impedance time from CK/CK#
tHZ
—tAC max
—
tAC max
ps
DQS low-impedance time from CK/CK#
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK#
tLZ(DQ)
2* tAC min
tAC max
2* tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
—
300
—
350
ps
DQ hold skew factor
tQHS
—
400
—
450
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
—tHP - tQHS
—ps
Write command to rst DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
tCK
Mode register set command cycle time
tMRD
2—2—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
—
0.35
—
tCK
Address and control input hold time
tIH
375
—
475
—
ps
Address and control input setup time
tIS
250
—
350
—
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page size products
tRRD
7.5
—
7.5
—
ns
Active to active command period for 2KB page size products
tRRD
10
—
10
—
ns
Four Activate Window for 1KB page size products
tFAW
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
ns
CAS# to CAS# command delay
tCCD
22
tCK
NOTE: AC timing parameters are based on Samsung components. Other DRAM manufacturers parameters may be different.
Continued on next page
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3HG264M72EEU534D6GG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED |
| WV3HG264M72EEU534D6MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED |
| WV3HG264M72EEU534D6SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED |
| WV3HG264M72EEU534D7IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL, Mini-DIMM |
| WV3HG264M72EEU534D7ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM UNBUFFERED, w/PLL, Mini-DIMM |
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