參數(shù)資料
型號(hào): WV3HG232M64EEU403D4SG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 64 DDR DRAM MODULE, 0.6 ns, DMA200
封裝: ROHS COMPLIANT, SODIMM-200
文件頁數(shù): 14/15頁
文件大?。?/td> 220K
代理商: WV3HG232M64EEU403D4SG
WV3HG232M64EEU-D4
January 2006
Rev. 1
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
ICC SPECIFICATION
Symbol
Proposed Conditions
665
534
403
Units
ICC0*
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
904
864
824
mA
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as ICC4W
984
944
864
mA
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
128
mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputsare
STABLE; Data bus inputs are FLOATING
480
400
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
560
480
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
560
480
mA
Slow PDN Exit MRS(12) = 1
240
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1200
1120
1040
mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1744
1464
1144
mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
1544
1344
1104
mA
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2720
2640
1560
mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
vre FLOATING; Data bus inputs are FLOATING
Normal
80
mA
ICC7*
Operating bank interleave read current;
All bank interleaVINg reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
2184
2104
mA
ICC specication is based on SAMSUNG components. Other DRAM manufactures specication may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reects all module ranks in this operating condition.
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