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參數(shù)資料
| 型號： | WV3HG128M72EER403D7SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA244 |
| 封裝： | ROHS COMPLIANT, MINIDIMM-244 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 200K |
| 代理商： | WV3HG128M72EER403D7SG |
WV3HG128M72EER-D7
October 2006
Rev. 1
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (continued)
VCC = +1.8V ± 0.1V
Parameter
Symbol
806
665
534
403
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Command
and
Address
Address and control input pulse width for each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tIS
TBD
200
250
ps
Address and control input hold time
tIH
TBD
275
375
475
ps
CAS# to CAS# command delay
tCCD
TBD
222
ps
ACTIVE to ACTIVE (same bank) command
tRC
TBD
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
ACTIVE to PRECHARGE command
tRAS
TBD
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge time
tDAL
TBD
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
ns
PRECHARGE ALL command period
tRPA
TBD
tRP + tCK
ns
LOAD MODE command cycle time
tMRD
TBD
222
tCK
CKE low to CK, CK# uncertainty
tDELAY
TBD
tIS+tCK+tIH
ns
Self
Refresh
REFRESH to Active or Refresh to Refresh command interval
tRFC
TBD
127.5 70,000 127.5 70,000 127.5 70,000
ns
Average periodic refresh interval
tREFI
TBD
7.8
μs
Exit self refresh to non-READ command
tXSNR
TBD
tRFC(MIN)
+ 10
tRFC(MIN)
+ 10
tRFC(MIN)
+ 10
ns
Exit self refresh to READ
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tlSXR
TBD
tIS
ps
ODT
ODT turn-on delay
tAOND
TBD
222222
tCK
ODT turn-on
tACN
TBD
tAC(MIN)
tAC(MAX)
+ 1000
tAC(MIN)
tAC(MAX)
+ 1000
tAC(MIN)
tAC(MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC(MIN)
tAC(MAX)
+
600
tAC(MIN)
tAC(MAX)
+
600
tAC(MIN)
tAC(MAX)
+
600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC(MIN) +
2000
2 x tCK +
tAC(MAX)
+ 1000
tAC(MIN) +
2000
2 x tCK +
tAC(MAX)
+ 1000
tAC(MIN) +
2000
2 x tCK +
tAC(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC(MIN) +
2000
2.5 x
tCK +
tAC(MAX) +
1000
tAC(MIN) +
2000
2.5 x
tCK +
tAC(MAX) +
1000
tAC(MIN) +
2000
2.5 x
tCK +
tAC(MAX)
+ 1000
ps
ODT to power-down entry latency
tANPD
TBD
333
tCK
ODT power-down exit latency
tAXPD
TBD
888
tCK
Power-Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
TBD
222
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
TBD
7-AL
6-AL
tCK
Exit precharge power-down to any non-READ command
tXP
TBD
222
tCK
CKE minimum high/low time
tCKE
TBD
333
tCK
AC specication is based on
SAMSUNG components. Other DRAM manufacturers specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3HG128M72EER534D7IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM |
| WV3HG128M72EER534D7ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM |
| WV3HG128M72EER534D7MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM |
| WV3HG128M72EER534D7SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM |
| WV3HG128M72EER665D7IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM |
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