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參數(shù)資料
| 型號： | WV3EG265M72EFSU335D4IN |
| 英文描述： | 1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| 中文描述： | 1GB的- 2x64Mx72 DDR內(nèi)存，無緩沖，鎖相環(huán)，F(xiàn)BGA封裝 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 183K |
| 代理商： | WV3EG265M72EFSU335D4IN |
WV3EG265M72EFSU-D4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
V
CC
= V
CCQ
= +2.5V ±0.2V
AC CHARACTERISTICS
PARAMETER
SYMBOL
MIN
Row cycle time
tRC
Refresh row cycle time
tRFC
Row active
tRAS
RAS# to CAS# delay
tRCD
Row precharge time
tRP
Row active to row active delay
tRRD
Write recovery time
tWR
Last data in to READ command
tWTR
CL = 2.5
t
CK (2.5)
CL =2
t
CK (2)
Clock high level width
t
CH
0.45
Clock low level width
t
CL
0.45
DQS-out access time from CK/CK#
t
DQSCK
-0.6
Output data access time from CK/CK#
tAC
-0.7
Data stobe edge to output data edge
t
DQSQ
Read preamble
tRPRE
Read postamble
tRPST
CK to vaild DQS-in
t
DQSS
0.75
DQS-in setup time
tWPRES
DQS-in hold time
tWPRE
0.25
DQS falling edge to CK rising-setup time
t
DSS
DQS falling edge to CK rising-hold time
tDHS
DQS-in high level width
tDQHS
0.35
DQS-in low level width
TDQSL
0.35
Address and control input setup time (fast)
tISF
0.75
Address and control input hold time (fast)
tIHF
0.75
Address and control input setup time (slow)
tISS
Address and control input hold time (slow)
tIHS
Data-out high impedance time from CK/CK#
tHZ
-0.70
Data-out low impedance time to CK/CK#
tLZ
-0.70
Mode register set cycle
tMRD
DQ & DM setup time to DQS
tDS
0.45
DQ & DM hold time to DQS
tDH
0.45
Control & address input pulse width
tIPW
DQ & DM input pulse width
tDIPW
1.75
Exit self refresh to non-read command
tXSNR
* AC specification is based on
SAMSUNG
components. Other DRAM manufactures specification may be different.
Continued on next page
335
262
265
UNITS
MAX
MIN
65
75
45
20
20
15
15
1
7.5
7.5
0.45
0.45
-0.75
-0.75
MAX
MIN
65
75
45
20
20
15
15
1
7.5
10
0.45
0.45
-0.75
-0.75
MAX
60
72
42
18
18
12
15
1
6
7.5
t
CK
ps
ps
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
t
CK
ns
t
CK
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70K
120K
120K
Clock cycle time
12
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
0.9
0.4
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
-0.75
15
0.5
0.5
2.2
1.75
75
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
-0.75
15
0.5
0.5
2.2
1.75
75
0
0.2
0.2
0.8
0.8
+0.70
+0.70
+0.75
+0.75
+0.75
+0.75
12
2.2
75
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG265M72EFSU335D4ING | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4IS | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
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