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參數(shù)資料
| 型號(hào)： | WV3EG265M72EFSU335D4IN |
| 英文描述： | 1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| 中文描述： | 1GB的- 2x64Mx72 DDR內(nèi)存，無緩沖，鎖相環(huán)，F(xiàn)BGA封裝 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 183K |
| 代理商： | WV3EG265M72EFSU335D4IN |
WV3EG265M72EFSU-D4
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
May 2006
Rev. 0
ADVANCED
I
CC
SPECIFICATIONS AND CONDITIONS
V
CC
, V
CCQ
= +2.5V ±0.2V
SYM
PARAMETER/CONDITION
MAX
UNITS
DDR333
@CL=2.5
1,270
DDR266
@CL=2
1,180
DDR266
@CL=2.5
1,180
I
CC0*
OPERATING CURRENT: One device bank; Active-Precharge; t
= t
(MIN); t
= t
(MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; t
= t
RC
(MIN);
t
CK
= t
CK
(MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; t
= t
(MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VI
N
= V
REF
for DQ,
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
t
CK
= t
CK
(MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; t
= t
RAS
(MAX); t
= t
(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, t
= minimum t
allowed; t
= t
CK
(MIN); Address and control inputs change only
during Active READ, or WRITE commands
mA
I
CC1*
1,540
1,450
1,450
mA
I
CC2P**
370
370
370
mA
I
CC2F**
820
820
820
mA
I
CC3P**
820
820
820
mA
I
CC3N**
1,090
1,090
1,090
mA
I
CC4R*
1,585
1,450
1,450
mA
I
CC4W*
1,675
1,495
1,495
mA
I
CC5**
I
CC6**
I
CC7*
t
REFC
= t
RFC
(MIN)
3,970
370
3,565
3,790
370
3,250
3,790
370
3,250
mA
mA
mA
Note: I
CC
specification is based on
SAMSUNG
components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in I
CC2P
(CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG265M72EFSU335D4ING | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4IS | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4M | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
| WV3EG265M72EFSU335D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, PLL, FBGA |
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