參數(shù)資料
型號： WV3EG264M72ESFR265D4-S
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封裝： SO-DIMM-200
文件頁數(shù)： 8/11頁
文件大?。?/td> 181K
代理商： WV3EG264M72ESFR265D4-S
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
0°C ≤ TCASE < +70°C; VCCQ = +2.5V ± 0.2V, VCC = +2.5V ± 0.2V
Parameter
Symbol
335
262
265
Unit
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
60
65
ns
Refresh row cycle time
tRFC
72
75
ns
Row active time
tRAS
42
70K
45
120K
45
120K
ns
RAS# to CAS# delay
tRCD
18
20
ns
Row precharge time
tRP
18
20
ns
Row active to Row active
tRRD
12
15
ns
Write recovery time
tWR
15
ns
Last data in to Read command
tWTR
111
tCK
Col. address to Col. address
tCCD
111
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput
tDQSQ
—
0.4
—
0.5
—
0.5
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRE
000
ns
DQS-in hold time
tWPRE
0.25
tCK
DQS falling edge to CK ris-
tDSS
0.2
tCK
DQS falling edge from CK
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input
tIS
0.75
0.9
ns
Address and Control Input
tIH
0.75
0.9
ns
Address and Control Input
tIS
0.8
1.0
ns
Address and Control Input
tIH
0.8
1.0
ns
Data-out high impedence time from CK/CK#
tHZ
+0.7
+0.75
ns
Data-out low impedence time from CK/CK#
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Input Slew Rate (for input)
tSL(I)
0.5
V/ns
Input Slew Rate (for I/O pins)
tSL(IO)
0.5
V/ns
Output Slew Rate (x4,x8)
Output Slew Rate Matching
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
Note: AC specications are based on Micron components. Other DRAM manufacturers specicaitons may be different.
相關(guān)PDF資料
PDF描述
W1D128M72R8A-5AL-FA1 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240
W1D128M72R8A-5AL-FA2 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240
W1D128M72R8A-5AP-FA1 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240
W1D128M72R8A-5AR-QB2 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240
W1D128M72R8B-5AP-PA1 128M X 8 DDR DRAM MODULE, 0.5 ns, DMA240
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
WV3EG264M72ESFR265D4-SG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
WV3EG264M72ESFR335D4-MG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
WV3EG264M72ESFR335D4-SG 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
WV3EG264M72ESFR-D4 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL
WV3EG265M64EFSU-D4 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL
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