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參數(shù)資料
| 型號： | WV3EG264M72ESFR265D4-S |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 181K |
| 代理商： | WV3EG264M72ESFR265D4-S |
WV3EG264M72ESFR-D4
August 2005
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
0°C TA 70°C
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage (for device with a nominal VCC of 2.5V)
VCC
2.3
2.7
I/O Supply voltage
VCCQ
2.3
2.7
V
I/O Reference voltage
VREF
0.49*VCCQ
0.51*VCCQ
V1
I/O Termination voltage (system)
VTT
VREF-0.04
VREF+0.04
V
2
Input logic high voltage
VIH(DC)
VREF+0.15
VCCQ+0.3
V
4
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
4
Input Voltage Level, CK and CK# inputs
VIN(DC)
-0.3
VCCQ+0.3
V
Input Differential Voltage, CK and CK# inputs
VID(DC)
0.3
VCCQ+0.6
V
3
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver); VOUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver); VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver); VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver); VOUT = VTT - 0.45V
IOL
9mA
Notes:
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specications are relative
to a VREF envelop that has been bandwidth limited to 200MHz.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.3
V
Voltage on VCC & VCCQ pin relative to VSS
VCC, VCCQ
-1.0 ~ 3.6
V
Storage Temperature
TSTG
-55 ~ +150
°C
Operating Temperature
TA
0 ~ +70
°C
Power dissipation – 1GB single mezzanine memory
PD
18
W
Short circuit current
IOS
50
mA
NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE
VCC 2.5V, VCCQ = 2.5V ±0.2V, TA = 25°C, f = 1MHz
Parameter
Symbol
Min
Max
Units
Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#,CAS#, WE# )
CIN1
911
pF
Input capacitance (CKE0, CKE1)
CIN2
911
pF
Input capacitance ( CS0#, CS1#)
CIN3
911
pF
Input capacitance ( CLK0, CLK0#)
CIN4
11
12
pF
Input capacitance ( DM0 ~ DM8)
CIN5
10
11
pF
Data & DQS input/output capacitance (DQ0~DQ63)
COUT1
10
11
pF
Data input/output capacitance (CB0 ~ CB7)
COUT2
10
11
pF
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG264M72ESFR265D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR335D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR335D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG264M72ESFR-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED, w/PLL |
| WV3EG265M64EFSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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