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參數(shù)資料
| 型號(hào)： | WV3EG216M64STSU335D4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | WV3EG216M64STSU335D4SG |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
August 2005
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
WV3EG216M64STSU-D4
ICC SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5 Max
Unit
Operating current
- One bank Active-
Precharge
ICC0*
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
288
mA
Operating current
- One bank operation
ICC1*
One bank open, BL=4, Reads - Refer to the following page for detailed test
condition
304
mA
Percharge power-
down standby current
ICC2P**
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
32
mA
Precharge Floating
standby current
ICC2F**
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
200
mA
Active power - down
standby current
ICC3P**
one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and
DM
80
mA
Active standby
current
ICC3N**
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC
= tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ, DQS and DM inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
312
mA
Operating current
- burst read
ICC4R*
Burst length = 2; reads; continguous burst; One bank active; address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; 50% of data changing at every burst; lout = 0mA
364
mA
Operating current
- burst write
ICC4W*
Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
408
mA
Auto refresh current
ICC5**
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
944
mA
Self refresh current;
CKE =< 0.2V
ICC6**
External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B
16
mA
Operating current
- Four bank operation
ICC7A*
Four bank interleaving with BL=4 -Refer to the following page for detailed test
condition
844
mA
NOTE:
ICC specication is based on
Nanya components. Other DRAM Manufacturers specication may be different.
* Value calculated as one module rank in this operation condition and other module rank in ICC2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG216M64STSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| WV3EG232M64EFSU262D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU262D4SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU265D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU265D4SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
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