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參數(shù)資料
| 型號： | WV3EG216M64STSU335D4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.7 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 281K |
| 代理商： | WV3EG216M64STSU335D4SG |
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
WV3EG216M64STSU-D4
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Parameter
Symbol
335
Unit
Min
Max
Row Cycle Time
tRC
60
ns
Refresh row cycle time
tRFC
72
ns
Row active
tRAS
42
120K
ns
RAS# to CAS# delay
tRCD
18
ns
Row precharge time
tRP
18
ns
Row active to row active delay
tRRD
12
ns
Write recovery time
tWR
15
ns
Last data into Read command
tWTR
1tCK
Clock cycle time
CL=2.5
tCK
612
ns
Clock high level width
tCH
0.45
0.55
tCK
Clock low level width
tCL
0.55
tCK
DQS-out access time from CK/CK#
tDQSCK
-0.6
+0.6
ns
Output data access time from CK/CK#
tAC
-0.7
+0.7
ns
Data strobe edge to output data edge
tDQSQ
-
0.45
ns
Read Preamble
tRPRE
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
tCK
DQS-in setup time
tWPRES
0ns
DQS-in hold time
tWPRE
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge to CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and control input setup time (fast)
tIS
0.75
ns
Address and control input hold time (fast)
tIH
0.75
ns
Address and control input setup (slow)
tIS
0.7
ns
Address and control input hold time (slow)
tIH
0.7
ns
Data-out high impedence time from CK/CK#
tHZ
-0.7
+0.7
ns
Data-out low impedence time from CK/CK#
tLZ
-0.7
+0.7
ns
Mode register set cycle time
tMRD
10
ns
DQ & DM setup time to DQS
tDS
0.4
ns
DQ & DM hold time to DQS
tDH
0.4
ns
Control & address input pulse width
tIPW
2.2
ns
DQ & DM input pulse width
tDIPW
1.75
ns
Exit self refresh o non-Read command
tXSNR
75
ns
Exit self refresh to Read command
tXSRD
200
tCK
Refresh interval time
tREFI
7.8
us
Output DQS valid window
tQH
tHP - tQHS
—ns
Clock half period
tHP
tCLMIN or tCHMIN
—ns
Data hold skew factor
tQHS
0.55
ns
DQS write postamble
tWPST
0.4
0.6
ns
Active Read with Auto precharge command
tRAP
18
ns
Auto precharge Write recovery + Precharge time
tRAL
(tWR/tCK) + (tRP/tCK)tCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG216M64STSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| WV3EG232M64EFSU262D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU262D4SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU265D4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
| WV3EG232M64EFSU265D4SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA |
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