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參數(shù)資料
| 型號： | WV3DG72256V75AD2SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | ROHS COMPLIANT, DIMM-168 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 253K |
| 代理商： | WV3DG72256V75AD2SG |
WV3DG72256V-AD2
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
OPERATING AC PARAMETER
Parameter
Symbol
133/100
Units
Notes
Min
Max
CLK cycle time
CAS latency = 3
tCC
7.5
1,000
ns
1
CAS latency = 2
–
CLK to valid output delay
CAS latency = 3
tSAC
5.4
ns
1, 2
CAS latency = 2
–
Output data hold time
CAS latency = 3
tOH
3
ns
2
CAS latency = 2
–
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-z
tSLZ
1ns
2
CLK to output in Hi-z
CAS latency = 3
tHZ
5.4
ns
CAS latency = 2
–
Notes: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time
compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter.
PRELIMINARY*
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WV3DG72256V-AD2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 SDRAM, REGISTERED |
| WV3DG7266V10D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V75D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V7D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
| WV3DG7266V-D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
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