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參數(shù)資料
| 型號(hào)： | WV3DG72256V-AD2 |
| 英文描述： | 2GB - 2x128Mx72 SDRAM, REGISTERED |
| 中文描述： | 2GB的- 2x128Mx72的SDRAM，注冊(cè) |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 264K |
| 代理商： | WV3DG72256V-AD2 |
WV3DG72256V-AD2
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2006
Rev. 0
AC OPERATING TEST CONDITIONS
V
CC
= 3.3V, 0°C
≤
T
A
≤
70°C
Parameter
AC Input level (V
IN
/V
IL
)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Units
V
V
ns
V
AC OPERATING TEST CONDITIONS
Parameter
Symbol
Value
133/100
15
20
20
45
100
65
2
2 CLK + t
RP
1
1
1
2
1
Units
Notes
Row active to row active delay
RAS# to CAS# delay
Row Precharge time
t
RRD(MIN)
t
RCD(MIN)
t
RP(MIN)
t
RAS(MIN)
t
RAS(MAX)
t
RC(MIN)
t
RDL(MIN)
t
DAL(MIN)
t
CDL(MIN)
t
BDL(MIN)
t
CCD(MIN)
ns
ns
ns
ns
μs
ns
CLK
—
CLK
CLK
CLK
CLK
ea
1
1
1
1
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
1
2
1
2
2
3
4
Number of valid output data
CAS Latency = 3
Cas Latency = 2
Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
3.3V
1220
870
Output
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=2.4V, I
OL
=-2mA
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
50pF
V
TT
=1.4V
50
Output
50pF
Z0 = 50
PRELIMINARY*
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| WV3DG7266V10D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB -2x32Mx72 SDRAM, UNBUFFERED, w/PLL |
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