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參數(shù)資料
| 型號(hào)： | WS512K32-55 |
| 英文描述： | 512Kx32 SRAM Module(512Kx32靜態(tài)RAM模塊（存取時(shí)間55ns）) |
| 中文描述： | 512Kx32 SRAM的模塊（512Kx32靜態(tài)內(nèi)存模塊（存取時(shí)間55ns）） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 150K |
| 代理商： | WS512K32-55 |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
°
C to +125
°
C)
FIG. 4
AC TEST CIRCUIT
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
Current Source
D.U.T.
C = 50 pf
I
OL
V
≈
1.5V
(Bipolar Supply)
Z
Current Source
OH
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
°
C to +125
°
C)
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
Unit
V
ns
V
V
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
-15*
Min
15
13
13
10
13
2
0
2
-17
-20
-25
-35
-45
-55
Units
Max
Min
17
15
15
11
15
2
0
2
Max
Min
20
15
15
12
15
2
0
3
Max
Min
25
17
17
13
17
2
0
4
Max
Min
35
25
25
20
25
2
0
4
Max
Min
45
35
35
25
35
2
5
5
Max
Min
55
50
50
25
40
2
5
5
Max
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
9
11
13
15
20
20
0
0
0
0
0
0
0
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2T, G1U and H1 packages. t
AS
minimum for the G4T package is 0ns.
Parameter
Symbol
-15*
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
15
17
20
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
17
20
25
35
45
55
0
0
0
0
0
0
0
15
8
17
9
20
10
25
12
35
25
45
25
55
25
2
0
2
0
2
0
2
0
4
0
4
0
4
0
12
12
12
12
12
12
12
15
15
20
20
20
20
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
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| WS512K32-55G2TCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
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