參數(shù)資料
型號: WM8718
廠商: Wolfson Microelectronics
英文描述: 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL
中文描述: 24位差分立體聲DAC,具有音量控制
文件頁數(shù): 16/27頁
文件大?。?/td> 284K
代理商: WM8718
WM8718
Production Data
w
PD Rev 4.1 March 2004
16
ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter.
Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8
Attenuation control bits. All attenuation registers are double latched allowing new values to be
pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on
any attenuation write will cause all pre-latched values to be immediately applied to the DAC
channels.
REGISTER
ADDRESS
0000
Attenuation
DACL
BITS
LABEL
DEFAULT
DESCRIPTION
[7:0]
LAT[7:0]
11111111 (0dB)
Attenuation data for Left Channel DACL in 0.5dB steps.
8
UPDATEL
0
Controls simultaneous update of all Attenuation Latches
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on all channels.
Attenuation data for Right channel DACR in 0.5dB steps.
[7:0]
RAT[7:0]
11111111 (0dB)
0001
Attenuation
DACR
8
UPDATER
0
Controls simultaneous update of all Attenuation Latches
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on all channels.
Table 4 Attenuation Register Map
Note:
1.
The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input
sample.
2.
Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise if the ZCDINIT
register bit has been set, (disabled).
DAC OUTPUT ATTENUATION
Registers DACR and DACL control the left and right channel attenuation. Table 9 shows how the
attenuation levels are selected from the 8-bit words.
DACX[7:0]
00(hex)
01(hex)
:
:
:
FE(hex)
FF(hex)
ATTENUATION LEVEL
dB (mute)
127.5dB
:
:
:
0.5dB
0dB
Table 5 Attenuation Control Levels
MUTE MODES
Figure 10 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)
begins to decay exponentially from the DC level of the last input sample. The output will decay
towards V
MID
with a time constant of approximately 64 input samples. When MUTE is de-
asserted, the output will restart almost immediately from the current input sample.
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