參數(shù)資料
型號： WM8718
廠商： Wolfson Microelectronics
英文描述： 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL
中文描述： 24位差分立體聲DAC，具有音量控制
文件頁數(shù)： 13/27頁
文件大小： 284K
代理商： WM8718
WM8718
Production Data
w
PD Rev 4.1 March 2004
13
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
SAMPLING
RATE
(LRCIN)
32kHz
44.1kHz
48kHz
96kHz
192kHz
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate
128fs
192fs
256fs
384fs
512fs
768fs
4.096
5.6448
6.144
12.288
24.576
6.144
8.467
9.216
18.432
36.864
8.192
11.2896
12.288
24.576
Unavailable Unavailable Unavailable Unavailable
12.288
16.9340
18.432
36.864
16.384
22.5792
24.576
Unavailable Unavailable
24.576
33.8688
36.864
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using a 3-wire (SPI-compatible) interface. In this
mode, SDIN is used for the program data, SCLK is used to clock in the program data and LATCH
is used to latch in the program data. The 3-wire interface protocol is shown in Figure 9.
LATCH
SCLK
SDIN
A6
D6
D7
D8
A0
A1
A2
A3
A4
A5
D1
D2
D3
D4
D5
D0
Figure 9 3-Wire Serial Control Interface
Notes:
1.
2.
A[6:0] are Control Address Bits
D[8:0] are Control Data Bits
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