參數(shù)資料
型號: WM8199SCDR
廠商: Wolfson Microelectronics
英文描述: 20MSPS 16-bit CCD Digitiser
中文描述: 20MSPS 16位數(shù)字化儀防治荒漠化公約
文件頁數(shù): 6/30頁
文件大小: 358K
代理商: WM8199SCDR
WM8199
Production Data
w
PD Rev 3.2 November 2003
6
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T
A
= 25
°
C, MCLK = 32MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion rate
Full-scale input voltage range
(see Note 1)
Input signal limits (see Note 2)
V
IN
Full-scale transition error
16
MSPS
Vp-p
Vp-p
V
mV
Max Gain
Min Gain
Gain = 0dB;
PGA[7:0] = 4B(hex)
Gain = 0dB;
PGA[7:0] = 4B(hex)
Min Gain
Max Gain
0.4
4.08
20
0
AVDD
Zero-scale transition error
20
mV
Differential non-linearity
Integral non-linearity
Channel to channel gain matching
Total output noise
DNL
INL
1.25
36
1
5
25
LSB
LSB
%
LSB rms
LSB rms
References
Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLC deviation
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity
Integral non-linearity
Step size
Output voltage
VRT
VRB
VRX
V
RTB
2.85
1.35
1.65
1.5
1.6
V
V
V
V
1.4
1.6
50
2
2
4
0.25
0.17
0.39
mA
μ
A
bits
V/step
V/step
V
VRLC = 0 to AVDD
AVDD=5V
AVDD=5V
1
V
RLCSTEP
V
RLCSTEP
V
RLCBOT
V
RLCBOT
0.26
V
V
RLCTOP
AVDD=5V
4.14
V
V
RLCTOP
2.81
V
25
mV
8
bits
LSB
LSB
mV/step
mV
mV
DNL
INL
0.1
0.25
2.02
-260
+260
0.5
1
Code 00(hex)
Code FF(hex)
Notes:
1.
Full-scale input voltage
denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
Input signal limits
are the limits within which the full-scale input voltage signal must lie.
2.
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