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參數(shù)資料
| 型號： | WM8199SCDR |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 20MSPS 16-bit CCD Digitiser |
| 中文描述： | 20MSPS 16位數(shù)字化儀防治荒漠化公約 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 358K |
| 代理商： | WM8199SCDR |
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WM8199
Production Data
w
PD Rev 3.2 November 2003
14
MCLK
VSMP
VS
R
S
/CL (CDSREF = 00)
R
S
/CL (CDSREF = 01)
R
S
/CL (CDSREF = 10)
R
S
/CL (CDSREF = 11)
Figure 10 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by R
s
at the same time as V
s
samples the video level in this
mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].
The gain characteristic of the WM8199 PGA is shown in Figure 11. Figure 12 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (3V).
0
1
2
3
4
5
6
7
8
0
64
128
192
256
Gain register value (PGA[7:0])
P
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
64
128
192
256
Gain register value (PGA[7:0])
P
s
Figure 11 PGA Gain Characteristic
Figure 12 Peak Input Voltage to Match ADC Full-scale Range
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order
(Red
→
Green
→
Blue
→
Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (3V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
相關PDF資料 |
PDF描述 |
|---|---|
| WM8199SCDS | 20MSPS 16-bit CCD Digitiser |
| WM8716 | High Performance 24-bit, 192kHz Stereo DAC |
| WM8716EDS | High Performance 24-bit, 192kHz Stereo DAC |
| WM8718 | 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL |
| WM8718EDS | 24 BIT DIFFERENTIAL STEREO DAC WITH VOLUME CONTROL |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WM8199SCDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:20MSPS 16-bit CCD Digitiser |
| WM8199SCDS/RV | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 16-Bit 20MSPS 3-Channel AFE RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| WM8199SCDS/V | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 16-Bit 20MSPS 3-Channel AFE RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| WM8200 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:40MSPS ADC with PGA |
| WM8200-10 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:40MSPS ADC with PGA |
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