參數(shù)資料
型號(hào)： WM8199
廠商： Wolfson Microelectronics
英文描述： 20MSPS 16-bit CCD Digitiser
中文描述： 20MSPS 16位數(shù)字化儀防治荒漠化公約
文件頁數(shù)： 4/30頁
文件大?。?/td> 358K
代理商： WM8199
WM8199
Production Data
w
PD Rev 3.2 November 2003
4
PIN DESCRIPTION
PIN
1
2
3
NAME
RINP
AGND2
DVDD1
TYPE
DESCRIPTION
Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if
used on every pixel. ACYC autocycles between R, G, B inputs.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Serial data input.
Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in two multiplexed formats as shown, under
the control of register MUXOP [1:0]
See ‘Output Formats’ description in Device Description section for further details.
Analogue input
Supply
Supply
4
5
6
OEB
VSMP
RLC/ACYC
Digital input
Digital input
Digital input
7
MCLK
Digital input
8
9
10
11
12
DGND
SEN
DVDD2
SDI
SCK
Supply
Digital input
Supply
Digital input
Digital input
8+8-bit
4+4+4+4-bit
B
d8
d9
d10
d11
A
d8
d9
d10
d11
d12
d13
d14
d15
B
d0
d1
d2
d3
d4
d5
d6
d7
A
C
d4
d5
d6
d7
D
13
14
15
16
17
18
19
20
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]/SDO
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d12
d13
d14
d15
d0
d1
d2
d3
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device
Description section for further details.
21
22
23
AVDD
AGND1
VRB
Supply
Supply
Analogue supply (5V). This must be operated at the same potential as DVDD1.
Analogue ground (0V).
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Blue channel input video.
Green channel input video.
Analogue output
24
VRT
Analogue output
25
VRX
Analogue output
26
VRLC/VBIAS
Analogue I/O
27
28
BINP
GINP
Analogue input
Analogue input
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