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參數(shù)資料
| 型號： | WM8170 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | 5.0 VOLT BI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR |
| 中文描述： | 3.3集成的信號處理器區(qū)陣CCD |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 453K |
| 代理商： | WM8170 |
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WM8170
Product Preview Rev 1.0
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
18
INPUT SIGNAL AMPLITUDE
The PGA gain setting allows the WM8170 to amplify the input video signal to be equal to the full-
scale input of the ADC. The minimum input video signal that can be scaled to the full-scale input of
the ADC is defined when the PGA is at the maximum gain. The maximum input video signal that can
be scaled to the full-scale input of the ADC is defined when the PGA is at minimum gain.
The minimum and maximum video input signal, which the WM8170 can accommodate, is set by a
combination of the TIMES2 and the V375 control bits. The input video conditions are summarised in
Table 1
TIMES2
V375
MAXIMUM VIN FOR FULL SCALE
ADC INPUT
PGA GAIN = 00(HEX)
1.0V
1.5V
0.5V
0.75V
MINIMUM VIN FOR FULL SCALE
ADC INPUT
PGA GAIN = FF(HEX)
40mV
60mV
20mV
30mV
0
0
1
1
0
1
0
1
Table 1 Input Signal Amplitude Conditions
ANALOGUE TO DIGITAL CONVERTER, DEVICE LATENCY AND OUTPUT TIMING
The 10-bit resolution ADC uses a pipelined architecture. The latency is the time delay between the
video sample (SHD) occurring and the corresponding valid output data being available. There are two
possible inputs that control the detailed timing of data output from the WM8170. These are SHD and
DCLK. The selection between SHD and DCLK is dependent on the control bit RETIME. If RETIME is
set low, then the output data on the D[9:0] pins is referenced to the rising edge of the SHD control
input. If RETIME is set high, the output data on the D[9:0] pins is reference to the rising edge of the
DCLK clock input. The use of RETIME allows the user to accurately control the output data timing,
which can ease the design of the interface between the WM8170 and following digital ASIC,
especially for high pixel rate systems.
With RETIME set low, the WM8170 latency is equal to eight pixel periods. With RETIME set high, the
WM8170 latency is equal to eight pixel periods plus the difference in timing between SHD and DCLK.
These two conditions are shown in Figure 14.
VIDEO
VIDEO SAMPLE,
SHD
REFERENCE
SAMPLE, SHP
D[9:0], RETIME=0
8 PIXEL PERIODS
V1
V2
V3
V4
DCLK
D[9:0], RETIME=1
V1
V2
V3
V4
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
Figure 14 WM8170 Latency
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