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WM8170
Product Preview Rev 1.0
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
15
INPUT BLANKING
In some cases the output signals from the CCD can be larger than the input stage of WM8170 could
normally handle without overload and saturation. To avoid this situation the Sample/Hold stage is
preceded by a pair of analogue switches, which can be used to block the analogue input signals at
PIN and DIN from passing to the Sample/Hold stage. These switches are turned on or off by placing
a high or low level on the PBLK pin respectively.
RESET LEVEL CLAMP OR AC COUPLING
The input video can be interfaced via a capacitor to the WM8170 by two methods. A Reset Level
Clamp facility is provided which can be used in both Sample and Hold and in CDS modes of
operation. The clamp switch is closed if a low level is applied to both CLPENB and CLPSWB digital
inputs. The clamp voltage, VCLP, can be programmed via the management interface to be equal to
VRB, VMID, or VRT. A typical use of the Reset Level Clamp facility using CDS is shown in Figure 12.
Alternatively, the CLPENB and CLPSWB digital inputs can be tied high, which will disable the Reset
Level Clamp switch, and the control bit ACINP set. This control bit connects an internal AC coupling
resistor to the DIN input, which allows the user to simply AC couple the analogue video signal into the
WM8170. If CDS is also used, then any drift on the WM8170 side of the coupling capacitor due to
input video DC content will be removed.
CLPENB
CLPSWB
RESET
S/H
SIGNAL
S/H
DIFFERENTIAL SIGNAL
TO GAIN BLOCK
SHD
SHP
PIN
PBLK
DIN
50k
ACINP
VMID
VCLP
VCLP
VMID
CORRELATED DOUBLE
SAMPLING
INVSHX
Figure 9 Input Sample/Hold and Reset Level Clamp Block Diagram
VIDEO
VIDEO SAMPLE, SHD
INVSHX=0
REFERENCE SAMPLE, SHP
INVSHX=0
V1
V2
V3
V4
Figure 10 Input Sample/Hold Timing, INVSHX = 0