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參數(shù)資料
| 型號： | WM8150 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | DIODE TVS 400W 5V UNI DIR |
| 中文描述： | 單通道12位獨聯(lián)體/防治荒漠化公約與4位寬輸出模擬前端 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 271K |
| 代理商： | WM8150 |
Production Data
WM8150
w
PD Rev 3.0 November 2002
9
TIMING CONTROL
R
S
S/H
4-BIT
RLC DAC
CL
+
+
-
TO OFFSET DAC
RLC
CDS
FROM CONTROL
INTERFACE
S/H
V
S
FROM CONTROL
INTERFACE
MCLK
VSMP
INPUT SAMPLING
BLOCK
CDS
C
IN
VINP
VRLC/
VBIAS
2
1
EXTERNAL VRLC
VRLCEXT
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
MCLK
VSMP
ACYC/RLC
or RLCINT
CL
(CDSREF = 01)
INPUT VIDEO
1
X
X
0
X
X
0
RGB
RGB
No RLC on this Pixel
RLC on this Pixel
Programmable Delay
RGB
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
s
/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 6.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WM8150_05 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output |
| WM8150CDS | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:SINGLE CHANNEL 12 BIT CIS/CCD AFE WITH 4 BIT WIDE OUTPUT |
| WM8150CDS/R | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output |
| WM8150CDSR | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:SINGLE CHANNEL 12 BIT CIS/CCD AFE WITH 4 BIT WIDE OUTPUT |
| WM8150SCDS | 功能描述:視頻 IC 12-Bit 6MSPS Single-Channel AFE RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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