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參數(shù)資料
| 型號(hào)： | WM2630IDT |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Octal 12-bit, Serial Input, Voltage Output DAC with Internal Reference |
| 中文描述： | 八路12位，串行輸入，電壓與內(nèi)部基準(zhǔn)輸出DAC |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 126K |
| 代理商： | WM2630IDT |
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Production Data
WM2630
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
9
SERIAL INTERFACE
INTERFACE MODES
The control interface can operate in two different modes:
In the microcontroller mode, FS needs to be held low until all 16 data bits have been transferred. If
FS is driven high before the 16
falling clock edge, the data transfer is cancelled. The DAC is
updated after a rising edge on FS.
In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16
th
falling clock edge.
SCLK
FS
X
DIN
D15
D14
D1
D0
X
E15
E14
E1
E0
X
F15
F14
X
Figure 7 Interface Timing in Microcontroller Mode
E1
SCLK
FS
X
DIN
D15
D14
D1
D0
E15
E14
E0
X
X
F15
F14
X
Figure 8 Interface Timing in DSP Mode
The operating mode is selected using pin 17 (MODE).
MODE PIN (17)
HIGH
LOW or unconnected
INTERFACE MODE
Microcontroller
DSP mode
Table 2 Interface Mode Selection
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the interface timing. The maximum serial clock rate is:
MHz
31
t
t
f
WL
WH
SCLK
1
+
min
min
max
=
=
Since a data word contains 16 bits, the sample rate is limited to
(
)
MHz
t
t
f
WL
WH
s
95
.
=
16
1
min
min
max
+
=
However, the DAC settling time to 12 bits accuracy limits the response time of the analogue output for
large input step transitions.
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