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參數(shù)資料
| 型號： | WM2626 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Low Power Dual 8-bit Serial Input DAC with Internal Reference |
| 中文描述： | 低功耗雙8位串行輸入DAC的內(nèi)部參考 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 109K |
| 代理商： | WM2626 |
WM2626
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
8
SOFTWARE CONFIGURATION OPTIONS
Table 2 shows the composition of a 16-bit data word. D11-D4 contains the 8-bit data word, and
D14-D13 hold the programmable options. Bits D15 and D12 are used for addressing the different
latches. D3 to D0 are unused and should be set to ZERO.
D15
R1
Table 2 Register Map
D14
SPD PWR
D13
D12
R0
D11
D10
D9
New DAC value (8 bits)
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
PROGRAMMABLE CONVERTER SPEED
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,
where typical settling time to within
±
0.5LSB of the final value is 0.8
μ
s. a ZERO puts the device into
the slow mode, where typical settling time is 2.8
μ
s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,
or fully powered up, a ONE configures the device into power down mode. When the power down
function is released the device reverts to the DAC code set prior to power down.
REGISTER ADDRESSING
Data received on the serial interface is routed according to the values of bits R1 and R0, as shown
in Table 3.
R1
(BIT D15)
0
0
1
1
Table 3 Latch Addressing
R0
(BIT D12)
0
1
0
1
REGISTER
Write data to DAC B and buffer
Write data to buffer
Write data to DAC A and update DAC B with buffer content
Write data to control register
To update both DACs simultaneously, the data intended for DAC B should first be stored in the
buffer. Subsequently, writing data to DAC A will automatically update the DAC B latch from the
buffer, so that the analogue output of both DACs will change at the same time.
When updating the two channels independently, all data written to the DAC B latch (R1 and R0 set
to ZERO) is also copied to the buffer. Thus the automatic update of DAC B when writing to DAC A
latch (R1=1, R0=0) does not change the DAC B data. Data should not be written only to the buffer
when operating in this mode.
The contents of the control register, shown below in Table 4, are used to program the internal
reference function.
D11
x
Table 4 Control Register Contents
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
D0
REF1 REF0
PROGRAMMABLE INTERNAL OR EXTERNAL REFERENCE
The reference can be sourced internally or externally under software control, as detailed in Table 5.
If an external reference voltage is applied to the REF pin, the device must be configured to accept
this. This will activate the reference input buffer, whose input resistance of 10M
(typical) makes
the reference input resistance independent of code.
REF1
0
0
1
1
REF0
0
1
0
1
FUNCTION
Use external reference
Use internal 1.024V reference
Use internal 2.048V reference
Use external reference
Table 5 Programmable Internal Reference
When using the on-chip reference, voltages of 1.024V or 2.048V are available. The internal
reference can source up to 1mA on the REF pin and can therefore be used as a system reference
for external components.
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