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參數(shù)資料
| 型號： | WM2618ID |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Connector assemblies, Network cables; |
| 中文描述： | 雙12位串行輸入電壓輸出DAC |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | WM2618ID |
WM2618
Production Data
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.1 October 2000
6
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital
data to analogue voltage levels (see Block Diagram). The output voltage is determined by the
reference input voltage and the input code according to the following relationship:
Output voltage =
(
)
4096
CODE
V
2
REF
INPUT
1111
OUTPUT
(
V
2
1111
1111
)
4096
:
)
4096
2048
4095
REF
:
1000
0000
0001
(
2049
V
2
REF
1000
0000
0000
(
)
REF
REF
V
4096
)
4096
:
)
4096
0V
V
2
=
0111
1111
1111
(
2047
V
2
REF
:
0000
0000
0001
(
1
V
2
REF
0000
0000
0000
Table 1 Binary Code Table (0V to 2V
REFIN
Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably
drive a 2k
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent
of code. The REFIN input resistance is 10M
and the REFIN input capacitance is typically
5pF. The reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input
data clocked in most significant bit first. The falling edge of the SCLK input shifts the data
into the input register. After 16 bits have been transferred, the next rising edge on SCLK or
NCS then transfers the data to the DAC latch. When NCS is high, input data cannot be
clocked into the input register (see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
f
SCLK
max =
MHz
20
t
t
1
+
min
WCL
min
WCH
=
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the
DAC settling time to 12 bits limits the update rate for large input step transitions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WM2623 | Low Power 8-bit Serial Input DAC |
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| WM2623ID | Low Power 8-bit Serial Input DAC |
| WM2626ID | Low Power Dual 8-bit Serial Input DAC with Internal Reference |
| WM2626CD | Low Power Dual 8-bit Serial Input DAC with Internal Reference |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WM2619 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:12-bit Parallel Input Voltage Output DAC |
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| WM2619IDT | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:12-bit Parallel Input Voltage Output DAC |
| WM2623 | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Low Power 8-bit Serial Input DAC |
| WM2623CD | 制造商:WOLFSON 制造商全稱:WOLFSON 功能描述:Low Power 8-bit Serial Input DAC |
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