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參數(shù)資料
| 型號： | WM2618ID |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Connector assemblies, Network cables; |
| 中文描述： | 雙12位串行輸入電壓輸出DAC |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | WM2618ID |
WM2618
Production Data
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.1 October 2000
4
Notes
:
1.
Integral non-linearity
(INL) is the maximum deviation of the output from the line between zero and full scale
(excluding the effects of zero code and full scale errors).
2.
Differential non-linearity
(DNL) is the difference between the measured and ideal 1LSB amplitude change of any
adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or
remains constant) as a change in digital input code.
3.
Zero code error
is the voltage output when the DAC input code is zero.
4.
Gain error
is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio
is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this
signal imposed on the zero code error and the gain error.
6.
Zero code error
and
Gain error
temperature coefficients are normalised to full scale voltage.
7.
Output load regulation
is the difference between the output voltage at full scale with a 10k
load and 2k
load. It
is expressed as a percentage of the full scale output voltage with a 10k
load.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply
current will increase.
8.
9.
Slew rate
results are for the lower value of the rising and falling edge slew rates.
10.
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising
and falling edges. Limits are ensured by design and characterisation, but are not production tested.
SERIAL INTERFACE
NCS
SCLK
DIN
D15
D14
D13
D12
D11
D0
t
SUCSS
t
WCL
t
WCH
t
SUCS1
t
SUCS2
t
HDCLK
t
SUDCLK
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
±
10%, V
REF
= 2.048V and VDD
= 3V
±
10%, V
REF
= 1.024V over recommended
operating free-air temperature range (unless noted otherwise)
SYMBOL
t
SUCSS
TEST CONDITIONS
Setup time NCS low before SCLK low
Setup time, falling edge of SCLK to rising edge of
NCS, external end of write
Setup time, rising edge of SCLK to falling edge of
NCS, start of next write cycle
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
MIN
5
TYP
MAX
UNIT
ns
t
SUSCS1
10
ns
t
SUSCS2
5
ns
t
WCL
t
WCH
t
SUDCLK
t
HDCLK
25
25
5
5
ns
ns
ns
ns
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