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參數(shù)資料
| 型號(hào)： | WM2618 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Dual 12-Bit Serial Input Voltage Output DAC |
| 中文描述： | 雙12位串行輸入電壓輸出DAC |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 125K |
| 代理商： | WM2618 |
Production Data
WM2618
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
7
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D0 contains the 12-
bit data word. D15-D12 hold the programmable options which are summarized in Table 3.
D15
D14
Program Bits
Table 2 Serial Word Format
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
New DAC value
PROGRAM BITS
D14
X
D15
1
D13
X
D12
X
DEVICE FUNCTION
Write to latch A with serial interface register data and
latch B updated with buffer latch data.
Write to latch B and double buffer latch.
Write to double buffer latch only.
12
μ
s settling time.
4
μ
s settling time.
Powered-up operation.
Power down mode.
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
1
0
1
X
X
X
X
Table 3 Program Bits D15 to D12 Function
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 12
μ
s or 4
μ
s, typical to within
±
0.5LSB of final value.
This is controlled by the value of D14. A ONE defines a settling time of 4
μ
s, a ZERO defines
a settling time of 12
μ
s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO configures the device as active, or
fully powered up, a ONE configures the device into power down mode. When the power
down function is released the device reverts to the DAC code set prior to power down.
FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12)
PURPOSE AND USE OF THE DOUBLE BUFFER
Normally only one DAC output can change after a write. The double buffer allows both DAC
outputs to change after a single write. This is achieved by the two following steps.
A double buffer only write is executed to store the new DAC B data without changing the
DAC A and B outputs.
Following the previous step, a write to latch A is executed. This writes the serial interface
register (SIR) data to latch A and also writes the double buffer contents to latch B. Thus
both DACs receive their new data at the same time and so both DAC outputs begin to
change at the same time.
Unless a double buffer only write is issued, the latch B and double buffer contents are
identical. Thus, following a write to latch A or B with another write to latch A does not change
the latch B contents.
Three data transfer options are possible. All transfers occur immediately after NCS goes high
(or on the sixteenth positive SCLK edge, whichever is earlier) and are described in the
following sections.
LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = X)
The serial interface register (SIR) data are written to latch A and the double buffer latch
contents are written to latch B. The double buffer contents are unaffected. This program bit
condition allows simultaneous output updates of both DACs.
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