參數(shù)資料
型號： WLA49VVA
廠商： National Semiconductor Corporation
元件分類： ADC
英文描述： Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
中文描述： 音頻子系統(tǒng)的雙模單聲道立體聲耳機(jī)和揚(yáng)聲器放大器的高效率和多功能模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 35/112頁
文件大小： 5017K
代理商： WLA49VVA
12.0 Status & Control Registers (Continued)
12.9 FURTHER NOTES ON PLL PROGRAMMING
The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 30 MHz with frequency errors
noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48 kHz and 44.1 kHz
sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC
a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is
available then the PLL can be used to obtain a clock that is accurate to within 1 Hz of the correct sample rate although this is
highly unlikely to be a problem.
TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates
F
in (MHz)
F
s (kHz)
M
N
P
PLL_M
PLL_N
PLL_N_MOD
PLL_P
F
out (MHz)
11
48
11
60
5
10
60
0
4
12
12.288
48
4
19.53125
5
3
19
17
4
12
13
48
13
60
5
12
60
0
4
12
14.4
48
9
37.5
5
8
37
16
4
12
16.2
48
27
100
5
26
100
0
4
12
16.8
48
14
50
5
13
50
0
4
12
19.2
48
13
40.625
5
12
40
20
4
12
19.44
48
27
100
6
26
100
0
5
12
19.68
48
21
64.03125
5
20
64
1
4
12
19.8
48
17
51.5
5
16
51
16
4
12
11
44.1
11
55.125
5
10
55
4
11.025
11.2896
44.1
8
39.0625
5
7
39
2
4
11.025
12
44.1
5
22.96875
5
4
22
31
4
11.025
13
44.1
13
55.125
5
12
55
4
11.025
14.4
44.1
12
45.9375
5
11
45
30
4
11.025
16.2
44.1
9
30.625
5
8
9
20
4
11.025
16.8
44.1
17
55.78125
5
16
30
25
4
11.025
19.2
44.1
16
45.9375
5
15
45
30
4
11.025
19.44
44.1
14
39.6875
5
13
39
22
4
11.025
19.68
44.1
21
47.0625
4
20
47
2
3
11.025
19.8
44.1
11
30.625
5
10
30
204
4
11.025
20134111
FIGURE 7. PLL Overview
LM4935
www.national.com
29
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