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參數(shù)資料
| 型號(hào)： | WL100/PR/FP1R |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, WIRELESS LAN CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | WL100/PR/FP1R |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
WL100
14
Dynamic Characteristics (see Figs. 15 and 16)
Data rate
Jitter tolerance
IRQ low to FIFO full/empty
ADC linearity, accuracy
ADC conversion time
RSSI input range
B_CLK frequency
I/O address to RD low
RD low to valid data
B_DATA set-up to WR low
I/O address to WR
RD duration
WR duration
DE6003 channel hop time
LOADB pulse width
Diversity decision time
RX/TX low to PAOFF high
PAOFF high to transmit data
PAOFF low to RX/TX high
WR to B_DATA hold time
RD to B_DATA hold time
Characteristic
Conditions
Units
C_CLK (MHz) to B_CLK (MHz) = 4:1, FL = 3
VREF = 123V
See Fig. 15
See Fig. 16 and Note 1
See Fig. 16
See Fig. 15
Value
15625
04
1
25
0
25
2
1
4
20
14
05
80
1000
375
160
2
24
32
16
96
kb/s
%
B_CLK cycles
LSB
s
V
MHz
ns
B_CLK cycles
s
ns
Symbol
(t1)
(t2)
(t3)
(t4)
(t5)
(t6)
(t7)
(t8)
(t9)
(t10)
(t11)
(t12)
(t13)
(t14)
Fig. 15 Typical controller bus timing
NOTE 1. Channel hop time, t7, is specified here as 80s (typ.) to be consistent with DE6003 requirements.
Min.
Typ. Max.
I /O ADDRESS
I /O READ CYCLE
I /O WRITE CYCLE
READ DATA
WRITE DATA
B_CLK
CS, ADDR
B_DATA
RD
WR
t1
t2
t5
t3
t4
t6
t1 = t4 = 25ns
t2 = 16ns (MAX)
t3 = 0ns (MIN)
t5 = t6 = 2 B_CLK CYCLES (MIN)
t13
t14
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| WL1015-L | 制造商:RFHIC 制造商全稱(chēng):RFHIC 功能描述:Wideband LNA |
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| WL102B | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Wireless Data Controller |
| WL102B/IG/TP1N | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Wireless Data Controller |
| WL102BC | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Wireless Data Controller |
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