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參數(shù)資料
| 型號： | WL100/PR/FP1R |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, WIRELESS LAN CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 306K |
| 代理商： | WL100/PR/FP1R |
WL100
7
CONFIGURATION REGISTERS
Tables 3, 4, and 5, together with Figs. 8 and 9, describe the
configuration registers of the WL100.
Table 3 describes the configuration registers that control
Clock Recovery and CCA; Table 4 describes the registers con-
trolling the Preamble Generator and Data Recovery mechanism
and Table 5 describes other programmable resources.
Bits
Register
Definition
JT (1:0)
NT (1:0)
BS (1:0)
ADDR 1A
ADDR 19
Jitter tolerance for the incoming data (maximum deviation from an ideal pulse.
when pulse is still considered valid). Three options.
Noise tolerance (number of occurrences of invalid data until the noise flag is
raised). Four options.
Bit stuffing algorithm. Four options.
9
Bits
Register
Definition
Fig.
ADDR 18
ADDR 13
ADDR 12
ADDR 19
ADDR 1A
ADDR 13
ADDR 14, 15, 16, 17
Number of Sync Words to be transmitted.
Number of bits in a Sync Word.
Sync Word bit pattern.
Number of Sync Words to be recovered before the Receiver is considered to be
in sync with the Transmitter.
Indicates if single bit errors are allowed before Frame Delimiter after
synchronisation has been achieved.
Number of bits in the Frame Delimiter.
Frame Delimiter bit pattern.
9
8
9
8
TSW (7:0)
BSW (2:0)
SW (7:0)
NSW (2:0)
BE (0)
BFW (4:0)
FW(31:0)
Table 4 Configuration registers controlling the Preamble Generator and the Data Recovery mechanism
Bits
Register
Definition
Fig.
ADDR 10,11
ADDR 19
ADDR 1A
Time limit for achieving synchronisation (0-216 C_CLK clock cycles).
Specifies required oversampling clock rate.
Specifies thresholds for Almost Full and Almost Empty FIFO flags.
8
9
ST (15:0)
DR(2:0)
FL(1:0)
Table 5 Other programmable resources
Table 3 Clock Recovery and CCA configuration registers
Fig.
Function
Manual
Auto
MAN (ADDR 00, bit 1)
ANTSEL (pin 52)
0
1
ANT 2 (ADDR 00, bit 2)
AUT 2 (ADDR 04, bit 7)
Table 6 Antenna selection table
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WL1015-L | 制造商:RFHIC 制造商全稱:RFHIC 功能描述:Wideband LNA |
| WL102 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Wireless Data Controller |
| WL102B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Wireless Data Controller |
| WL102B/IG/TP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wireless Data Controller |
| WL102BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Wireless Data Controller |
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