參數(shù)資料
型號： WJLXT972MLC.A4
廠商： CORTINA SYSTEMS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： ROHS COMPLIANT, LQFP-48
文件頁數(shù)： 61/92頁
文件大小： 1257K
代理商： WJLXT972MLC.A4
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
64
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 27 lists the 100BASE-TX characteristics.
Table 28 lists the 10BASE-T characteristics.
Table 29 lists the 10BASE-T link integrity timing characteristics.
Table 27. 100BASE-TX Transceiver Characteristics
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
Peak differential output voltage
VP
0.95
–
1.05
V
Note 2
Signal amplitude symmetry
Vss
98
–
102
%
Note 2
Signal rise/fall time
TRF
3.0
–
5.0
ns
Note 2
Rise/fall time symmetry
TRFS
–
0.5
ns
Note 2
Duty cycle distortion
DCD
35
50
65
%
Offset from 16 ns pulse
width at 50% of pulse
peak
Overshoot/Undershoot
VOS
––
5
%
–
Jitter (measured differentially)
–
1.4
ns
–
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
testing.
2. Measured at the line side of the transformer, line replaced by 100
Ω(+/-1%) resistor.
Table 28. 10BASE-T Transceiver Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmitter
Peak differential output
voltage
VOP
2.2
2.5
2.8
V
With transformer, line
replaced by 100
Ω
resistor
Transition timing jitter added
by the MAU and PLS
sections
–0
2
11
ns
After line model
specified by IEEE
802.3 for 10BASE-T
MAU
Receiver
Receive Input Impedance
ZIN
––
22
k
Ω
–
Differential Squelch
Threshold
VDS
300
420
585
mV
–
Table 29. 10BASE-T Link Integrity Timing Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Time Link Loss Receive
TLL
50
–
150
ms
–
Link Pulse
TLP
2
–
7
Link Pulses
–
Link Min Receive Timer
TLR MIN
2–
7
ms
–
Link Max Receive Timer
TLR MAX
50
–
150
ms
–
Link Transmit Period
Tlt
8
–
24
ms
–
Link Pulse Width
Tlpw
60
–
150
ns
–
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
testing.
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