參數(shù)資料
型號(hào)： WJLXT972MLC.A4
廠商： INTEL CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP48
封裝： ROHS COMPLIANT, LQFP-48
文件頁(yè)數(shù)： 72/92頁(yè)
文件大小： 1257K
代理商： WJLXT972MLC.A4
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
74
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 33. Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Table 39. Intel LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
RESET_L pulse width
t1
10
–
ns
–
RESET_L recovery delay
2
t2
–
300
μs–
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance. The PHY comes out of reset after a delay of no more than 300
μs. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300
μs before accessing the MDIO port.
t2
RESET_L
MDIO, and
so on
t1
B3495-01
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