- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140370 > WEDPZ512K72V-100BC (WHITE ELECTRONIC DESIGNS CORP) 512K X 72 ZBT SRAM, 5 ns, PBGA152 PDF資料下載
參數(shù)資料
| 型號： | WEDPZ512K72V-100BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 72 ZBT SRAM, 5 ns, PBGA152 |
| 封裝： | 17 X 23 MM, PLASTIC, BGA-152 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 0K |
| 代理商： | WEDPZ512K72V-100BC |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WEDPZ512K72V-XBX
February 2009
Rev. 9
OUTPUT LOAD (A)
OUTPUT LOAD (B)
FOR tlzc, tlzoe, thzoe, and thzc
Dout
Zo=50Ω
RL=50Ω
VL=1.5V
50pF*
Dout
353Ω/1538Ω
5pF*
+3.3V for 3.3V I/O, +2.5V for 2.5V I/O
319Ω/1667Ω
*Including Scope and Jig Capacitance
AC TEST CONDITIONS
Parameter
Value
Input Pulse Level
0 to 3.6V
Input Rise and Fall Time
1.0V/ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Output Load (A & B)
AC CHARACTERISTICS
-55°C ≤ TA ≤ + 125°C
Parameter
Symbol
150MHz
133MHz
100MHz
Units
Min
Max
Min
Max
Min
Max
Clock Time
tCYC
6.7
7.5
10.0
ns
Clock Access Time
tCD
—
3.8
—
4.2
—
5.0
ns
Output enable to Data Valid
tOE
—
3.8
—
4.2
—
5.0
ns
Clock High to Output Low-Z
tLZC
1.5
—
1.5
—
1.5
—
ns
Output Hold from Clock High
tOH
1.5
—
1.5
—
1.5
—
ns
Output Enable Low to output Low-Z
tLZOE
0.0
—
0.0
—
0.0
—
ns
Output Enable High to Output High-Z
tHZOE
—
3.0
—
3.5
—
3.5
ns
Clock High to Output High-Z
tHZC
—
3.0
—
3.5
—
3.5
ns
Clock High Pulse Width
tCH
2.5
—
2.5
—
3.0
—
ns
Clock Low Pulse Width
tCL
2.5
—
2.5
—
3.0
—
ns
Address Setup to Clock High
tAS
1.5
—
1.5
—
1.5
—
ns
CKE Setup to Clock High
tCES
1.5
—
1.5
—
1.5
—
ns
Data Setup to Clock High
tDS
1.5
—
1.5
—
1.5
—
ns
Write Setup to Clock High
tWS
1.5
—
1.5
—
1.5
—
ns
Address Advance to Clock High
tADVS
1.5
ns
Chip Select Setup to Clock High
tCSS
1.5
ns
Address Hold to Clock high
tAH
0.5
—
0.5
—
0.5
—
ns
CKE Hold to Clock High
tCEH
0.5
-
0.5
—
0.5
—
ns
Data Hold to Clock High
tDH
0.5
—
0.5
—
0.5
—
ns
Write Hold to Clock High
tWH
0.5
—
0.5
—
0.5
—
ns
Address Advance to Clock High
tADVH
0.5
—
0.5
—
0.5
—
ns
Chip Select Hold to Clock High
tCSH
0.5
—
0.5
—
0.5
—
ns
NOTES:
1.
All Address inputs must meet the specied setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CSx# is
sampled valid. All other synchronous inputs must meet the specied setup and hold times whenever this device is chip selected.
2.
Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3.
A write cycle is dened by WE# low having been registered into the device at ADV Low. A Read cycle is dened by WE# High with ADV Low.
Both cases must meet setup and hold times.
VL = 1.5V for 3.3V I/O
VCCQ/2 for 2.5V I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS128K32-20G1UC | 128K X 32 MULTI DEVICE SRAM MODULE, 20 ns, CQFP68 |
| WS128K32-25G1TCA | 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68 |
| WS128K32-25G1TQA | 128K X 32 MULTI DEVICE SRAM MODULE, 25 ns, CQFP68 |
| WS128K32-35G1UM | 128K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| WS128K32-55G1TMA | 128K X 32 MULTI DEVICE SRAM MODULE, 55 ns, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPZ512K72V-100BI | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 3.3V, 100MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72V-100BM | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 3.3V, 100MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72V-133BC | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 3.3V, 133MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72V-133BI | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 3.3V, 133MHZ, 152 BGA 17MM X 23M - Bulk |
| WEDPZ512K72V-133BM | 制造商:Microsemi Corporation 功能描述:512K X 72 ZBL SSRAM MODULE, 3.3V, 133MHZ, 152 BGA 17MM X 23M - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。